Date of Award

Spring 2025

Project Type

Dissertation

Program or Major

Electrical and Computer Engineering

Degree Name

Doctor of Philosophy

First Advisor

Qiaoyan QY Yu

Second Advisor

Md Shaad MM Mahmud

Third Advisor

Dean DS Sullivan

Abstract

Field Programmable Gate Arrays (FPGA) have gained popularity and usage in recent years, and they have been widely used in mission-critical applications. Due to its popularity, the security of FPGA has become a big concern. Most existing research on FPGA security focuses on hardware Trojans, side-channel attacks, and reverse engineering. The existing FPGA countermeasures against the attacks above are typically limited to the FPGA systems implemented in the old FPGA utilization model. An increase in cloud-based FPGA providers, third-party accelerator suppliers, and open-source FPGAdesign tools has changed the FPGA utilization model, which requires new security measures for modern FPGAs. This thesis investigates emerging security threats in modern FPGA usage, mainly focusing on FPGA Computer-Aided Design (CAD) tools and multi-tenant FPGA environments. This thesis also proposes dynamic, adaptive countermeasures to protect and update FPGA systems against traditional and emerging attacks. FPGA CAD tool is one of the entities in the FPGA design flow. The state-of-the-art efforts on FPGA CAD tool only protect FPGA systems from IP piracy and hardware tampering rather than improving attack resilience against CAD tool attacks. This thesis identifies and demonstrates critical security flaws in FPGA CAD tools related to IP encryption, design isolation, and current design countermeasure implementation. To thwart attacks originating from CAD tools, a dynamic partial reconfiguration-enabled design obfuscation (DPReDO) method is developed to strengthen the existing design obfuscation method by modifying the FPGA bitstream at runtime. DPReDO significantly reduces CAD Trojan hit rates by 80% compared to static obfuscation methods. Additionally, the increasing prevalence of FPGA-as-a-Service (FaaS) and cloud-based FPGA accelerators exposes multi-tenant FPGAs to remote, exploitable fault attacks, particularly Power Waster Circuit (PWC)-based attacks. Existing countermeasures fall short in addressing multi-source attacks and non-combinatorial PWCs. To address this, the thesis proposes Signal-Slowdown-based Fault Attack Mitigation (S2FAM), a dynamic approach that achieves a 100% detection rate for combinatorial and non-combinatorial PWC attacks. S2FAM also outperforms existing techniques in attack localization with a 25.2% improvement in precision. By analyzing security risks introduced by modern FPGA utilization models, this thesis establishes a comprehensive threat landscape and proposes novel, adaptive countermeasures that enhance the resilience of FPGA-based systems.

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