Date of Award

Winter 2019

Project Type


Program or Major

Electrical and Computer Engineering

Degree Name

Master of Science

First Advisor

Michael J Carter

Second Advisor

Nicholas J Kirsch

Third Advisor

Richard A Messner


Electrical data communication links less than 10 meters long are increasing link rates at a steady pace. As link rate increases, timing tolerances become more important to ensure low bit error rates (BER). Ensuring high performance links in scenarios with large amounts of crosstalk requires the characterization of transmitter output jitter (TOJ). Some jitter models are incapable of effectively separating Gaussian random jitter from jitter caused by crosstalk. To overcome this, IEEE 802.3-2018 Clause 92 100GBASE-CR4 defines TOJ tests using the dual-Dirac (��-��) model. Additionally the 100GBASE-CR4 TOJ test definition separates out components of jitter by selecting isolated edges in a test pattern to be sampled. Applying the ��-�� model to specific edges in a test pattern is not widely present in other jitter test methodologies. In this thesis the IEEE 802.3-2018 Clause 92 TOJ tests are implemented, and issues related to measurement time, captured data size, and measurement accuracy are addressed. A set of measurements were taken of a signal generator with a set of expected worst case jitter components applied to the signal. These measurements are explored to validate the implementation and examine limitations of the test definition. (316347 kB)
Waveform raw data used in convergence test (13871 kB)
TOJ raw data present in appendices